Amplifiers, such as high-power amplifiers used in the base stations of wireless communication systems, typically exhibit non-linearity over their operating ranges. This non-linearity can result in noise that can corrupt or otherwise interfere with the communications. To address this problem, additional circuitry may be added to an amplifier in an attempt to linearize the effective amplifier response. Conventional techniques for linearizing amplifiers typically involve pre-distortion compensation and/or feed-forward distortion compensation.
In amplifier linearization based on pre-distortion compensation, the input signal that is to be amplified is pre-distorted prior to being applied to the amplifier in order to adjust the input signal based on known or detected non-linearities in the amplifier transfer function. In feed-forward distortion compensation, an error signal is fed forward and combined with the output of the amplifier to adjust the output signal for non-linearities in the amplifier transfer function.
FIG. 1 shows a high-level block diagram of a linearized amplifier circuit 100 according to the prior art. Amplifier circuit 100 utilizes feed-forward distortion compensation to linearize the response of a high-power amplifier (HPA) 112. Amplifier circuit 100 has a main signal path and an error signal path. The main signal path includes phase adjuster 104, amplitude adjuster 106, HPA 112, tap 114, high-power delay line 116, and coupler 118, while the error signal path includes low-power delay line 120, coupler 122, phase adjuster 126, amplitude adjuster 128, and error amplifier (EA) 130. In addition, amplifier circuit 100 includes splitter 102, pilot generator 108, coupler 110, tap 124, fixed attenuator 132, microprocessor controller 134, nulling circuits 136 and 140, log amps 138 and 142, receiver circuit 144, and tap 146.
In operation, an input signal (e.g., a radio frequency (RF) signal) is split at splitter 102, with portions of the input signal applied to the main and error signal paths, respectively. In the main signal path, the phase and/or amplitude of the signal from splitter 102 are (optionally) adjusted by phase adjuster 104 and/or amplitude adjuster 106, respectively, prior to being applied to HPA 112. If pilot generator 108 is activated, then a pilot signal is injected into the signal at coupler 110 prior to being applied to HPA 112. A portion of the amplified signal generated by HPA 112 is tapped off at tap 114 and attenuated through fixed attenuator 132. The remaining portion of the amplified signal from HPA 112 is time-aligned at delay line 116 to compensate for latency in the error signal path. A feed-forward error-compensation signal (described below) from EA 130 is subtracted from the delayed, amplified signal from delay line 116 at coupler 118 and the resulting error-compensated signal is provided as the output signal from amplifier circuit 100. Receiver circuit 144 monitors a sample of the output signal received from tap 146.
In the error signal path, the signal from splitter 102 is delayed by delay line 120 (to compensate for the timing of the corresponding portion of the main signal path). At coupler 122, the signal received from attenuator 132 is subtracted from the delayed signal from delay line 120 to generate an error signal. Phase adjuster 126 and/or amplitude adjuster 128 (optionally) adjust the phase and/or amplitude, respectively, of the error signal prior to application to EA 130. The amplified output from EA 130 is the feed-forward error-compensation signal that is subtracted from the delayed, amplified signal from delay line 116 at coupler 118 to generate the output signal.
A portion of the error signal from coupler 122 is tapped by tap 124, detected by log amp 138, and processed by microprocessor controller 134, which uses that detected signal to control the operations of nulling circuit 136, which in turn generates the control signals for phase adjuster 104 and amplitude adjuster 106. Similarly, a portion of the output signal from coupler 118 is tapped by tap 146, processed by receiver circuit 144, detected by log amp 142, and processed by microprocessor controller 134, which uses that detected signal to control the operations of nulling circuit 140, which in turn generates the control signals for phase adjuster 126 and amplitude adjuster 128.
As indicated in FIG. 1, amplifier circuit 100 has two loops: a carrier cancellation loop (i.e., Loop 1) and an error cancellation loop (i.e., Loop 2). According to the prior art, amplifier circuit 100 is tuned by first tuning the carrier cancellation loop and then tuning the error cancellation loop. In particular, the carrier cancellation loop is tuned by applying an input signal to amplifier circuit 100 (with pilot generator 108 turned off) and using phase adjuster 104 and/or amplitude adjuster 106 to adjust the phase and/or amplitude of the applied signal until the power of the error signal detected by log amp 138 is minimized.
After the carrier cancellation loop has been tuned and with the input signal typically still present, the error cancellation loop is then tuned by (i) injecting a known pilot signal (e.g., one or more continuous wave (CW) signals or a spread-spectrum signal) from pilot generator 108 at coupler 110 and (ii) with phase adjuster 104 and amplitude adjuster 106 locked in a tuned state, using phase adjuster 126 and/or amplitude adjuster 128 to adjust the phase and/or amplitude of the error signal until the power of the pilot signal detected by receiver circuit 144 is minimized (e.g., ideally zero).
In order to maintain tuning of a real-world amplifier system in which operating characteristics vary over time with changes in the input signal, the ambient temperature and humidity, and the like, the system-tuning process consisting of first tuning the carrier cancellation loop followed by the tuning of the error cancellation loop is typically repeated to dynamically adjust the operations of amplifier circuit 100.
In order for receiver circuit 144 to be able to distinguish the presence of the amplified pilot signal from the amplified input signal, the pilot signal injected at coupler 110 must be different in some way from the input signal. In some prior art implementations, pilot generator 108 is designed to generate the pilot signal as a CW signal having a frequency different from those frequencies contained in the input signal. In this case, receiver circuit 144 is typically implemented as a narrow-band detector that is able to detect the presence of the amplified CW pilot signal in the otherwise wide-band output signal.